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Architectures of high-performance 3D graphics accelerators
Author
Title
Architectures of high-performance 3D graphics accelerators [videorecording] / Kurt Akeley.
Published
Stanford, CA : University Video Communications, c1992.
Physical Description
1 videocassette (53 min.) : sd., col. ; 1/2 in.
Notes
VHS format.
"Recorded 4/10/92".
Sponsored by Silicon Graphics, Inc.
At head of title: Distinguished lecture series IV.
Summary
Because the computations required to support interactive 3D graphics are both substantial and easily parallelized, special purpose hardware is often used. This lecture describes the calculations required for 3D graphics, and considers various parallel hardware architectures used to implement them. Issues that constrain these systems, such as interprocessor communication, load balancing, and context switching, are contrasted for different architectures.
Format
Video & Film
Language
English
Added to Catalog
June 01, 2002
Series
Leaders in computer science and electrical engineering
Subjects
Also listed under
Silicon Graphics Computer Systems.
Bookmark As
Citation
